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User’s Manual
ECM-3711 Series User’s Manual
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1.6.2 VIA CN700 & VT8251
The CN700 implements a deep In-Order Queue to improve system performance for
multi-threaded software applications. DBI and V4 bus protocol are supported which
effectively reduce overall system power consumption. The AGP controller is AGP v3.5
compliant with up to 2.1GB/second data transfer rate. It supports pseudo-synchronous
AGP and CPU interface to maximize system performance. Deep read and write (256 bytes
each) FIFO are integrated for optimal bus utilization and minimum data transfer latency.
The CN700 supports 64-bit memory data bus access and the DDR DRAM interface allows
zero wait-state data transfer bursting between the DRAM and memory controller’s data
buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 /
256 / 512 / 1024 Mb SDRAM in x 8 or x16 configurations. The DRAM controller can run
either synchronous or pseudo-synchronous with the host CPU bus. The CN700 North
Bridge interfaces to the South Bridge through a high speed (up to 533 MB/sec) 8x 66 MHz
Data Transfer interconnect bus called V-Link interface. Deep pre-fetch and post-write
buffers are included to allow for concurrent CPU and V-Link operation. System Power
Management for sophisticated power management, the CN700 supports dynamic CKE
control to minimize DDR SDRAM power consumption during normal system state (S0). A
separate suspend power plane is implemented for the memory control logic for
Suspend-to-DRAM state. The CN700 graphics controller implements dynamic clock gating
for inactive functions to achieve maximum power saving. The system can be switched to
standby or suspend states to further reduce power consumption when idle. VESA DPMS
(Display Power Management Signaling) CRT power-down is supported. 3D Graphics
Engine Featuring an integrated 128-bit 3D graphics engine, the CN700 North Bridge
utilizes a single cycle architecture that provides high performance along with superior
image quality. Several new features enhance the 3D architecture, including single-pass
multitexturing, anisotropic filtering, and an 8-bit stencil buffer. The chip also offers the
industry’s only simultaneous usage of single-pass multitexturing and single-cycle trilinear
filtering – enabling stunning image quality without performance loss. Image quality is further
enhanced with true 32-bit color rendering throughout the 3D pipeline to produce more vivid
and realistic images. The advanced triangle setup engine provides realistic user
experiences in games and other interactive 3D applications. The 3D engine is optimized for
AGP texturing from system memory.