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USB 2.0 Hi-Speed 2-Port Hub Controller
Datasheet
SMSC USB2512A 27 Revision 1.96 (07-11-08)
DATASHEET
4.3.5 Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch
the SCLK.
4.3.6 SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
in the “Timing Diagram” section.
4.3.7 Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed
immediately by a STOP field.
4.3.8 SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
4.3.8.1 Undefined Registers
The registers shown in Table 4.1 are the defined registers in the Hub. Reads to undefined registers
return 00h. Writes to undefined registers have no effect and do not return an error.
4.3.8.2 Reserved Registers
Unless otherwise instructed, only a ‘0’ may be written to all reserved registers or bits.
4.4 Default Configuration Option:
The SMSC Hub can be configured via its internal default configuration. (please see Section 4.2.1,
"Internal Register Set (Common to EEPROM and SMBus)" for specific details on how to enable default
configuration.)
Please refer to Table 4.1 for the internal default values that are loaded when this option is selected.
4.5 Default Strapping Options:
The USB2512A can be configured via a combination of internal default values and pin strap options.
Please see Table 3.1 and Table 3.2 for specific details on how to enable the default/pin-strap
configuration option.
The strapping option pins only cover a limited sub-set of the configuration options. The internal default
values will be used for the bits & registers that are not controlled by a strapping option pin. Please
refer to Table 4.1 for the internal default values that are loaded when this option is selected.
4.6 Reset
There are two different resets that the Hub experiences. One is a hardware reset (either from the
internal POR reset circuit or via the RESET_N pin) and the second is a USB Bus Reset.
4.6.1 Internal POR Hardware Reset
All reset timing parameters are guaranteed by design.