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Hi-Speed USB Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-15-07) 36 SMSC USB3280
DATASHEET
Notes:
T0 may be up to 4ms after HS Reset T0.
The SIE must use LINESTATE to detect the downstream port chirp sequence.
Due to the assertion of the HS termination on the host port and FS termination on the device port,
between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are
less than FS signaling levels.
8.10 HS Detection Handshake – Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down. Figure 8.6 shows how CLKOUT is used to control the duration of the
chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLKOUT
signal until it is "usable" (where "usable" is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).
The first transition of CLKOUT occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to
ensure a 1ms minimum duration. If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If
CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first
CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete
before T3. Once the Chirp K is completed (T3) the SIE can begin looking for host chirps and use
CLKOUT to time the process. At this time, the device follows the same protocol as in Section 8.9,
"HS Detection Handshake – HS Downstream Facing Port" for completion of the High Speed
Handshake.