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Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the capability of the Intel 5520 platform, the X8DT6/X8DT6-F/X8DTE/
X8DTE-F motherboard provides the performance and feature set required for
dual-processor-based high-end servers optimized for High Performance Comput-
ing (HPC), Clustering, and intensive applications. The 5520 platform consists of
the 5500/5600 Series (LGA 1366) processor, the 5520 (IO Hub), and the ICH10R
(South Bridge). With the QuickPath Interconnect (QPI) controller built in, the
5500/5600 Series Processor is the fi rst DP platform that offers the next genera-
tion point-to-point system interconnect interface that replaces the current Front
Side Bus Technology, substantially enhancing system performance with increased
bandwidth and scalability.
The 5520 IO Hub connects to each processor through an independent QuickPath
Interconnect link. Each link consists of 20 pairs of unidirectional differential lanes
for data transferring in addition to a differential forwarded clock. A full-width
QuickPath interconnect link pair provides 84 signals. Each processor supports two
QuickPath links, one going to the other processor and the other to the 5520.
The 5520 platform supports up to 36 PCI Express Gen2 lanes, peer-to-peer read
and write transactions. The ICH10R provides up to 6 PCI-Express ports, six SATA
ports and eight USB connections.
In addition, the 5520 platform also offers a wide range of RAS (Reliability, Avail-
ability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC),
parity protection, out-of-band register access via SMBus, memory mirroring, and
Hot-plug support on the PCI-Express Interface.
Main Features of the 5500/5600 Series Processor and the
5520 Chipset
Four processor cores in each processor with 8MB shared cache among cores•
Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer •
rate in each direction
Virtualization Technology, Integrated Management Engine supported
•
Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and •
Concurrent bi-directional traffi c
Error detection via CRC and Error correction via Link level retry
•