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Chapter 4 – SocketModem Parallel Interface – A Programmer’s Description
SocketModem Global MT5634SMI Developer’s Guide 16
Chapter 4 – SocketModem Parallel
Interface – A Programmer’s
Description
SocketModem Parallel Interface Internal Registers
The SocketModem parallel interface is a mimic of a 16C550A UART. It is similar to the MIMIC interface used in
the Zilog Z80189. The SocketModem mimic (MMM) takes advantage of this standard interface while replacing
the serial to parallel data transfer with a less complicated parallel to parallel data transfer.
The MMM interface controls an 8-bit parallel data transfer which is typically interrupt driven. Interrupts usually
indicate one or both of two conditions: (1) the receive (RX) FIFO has either reached a trigger level or time-out
condition and needs to be emptied and/or (2) the transmit (TX) FIFO is empty and waiting for more data from the
Host. An interrupt can also be triggered by a change in the modem status register (i.e., loss of carrier) or by the
occurrence of errors in the line status register (overrun, parity, framing, break detect).
In addition to the receive and transmit FIFOs, there are twelve other control/status registers called the MMM
register set which can be accessed through this interface.
SocketModem MIMIC (MMM) Operation
Data flow through MMM is bi-directional. Simultaneously, data can flow from the host through the transmit FIFO
to the SocketModem controller, and data can flow from SocketModem controller through the receive FIFO to the
Host. In the receive path, 8-bit data is asynchronously received (from the SocketModem controller) by the
receive FIFO where it is stored along with associated three error bits. The error bits must arrive (via a
SocketModem controller I/O write to MMM shadow line status register) prior to receiving the actual data bits. The
error bits are then temporarily stored so they may be written, with associated data bits, to the 11-bit wide RX
FIFO.
After every data write, the RX FIFO write pointer is incremented. RX FIFO trigger levels, data ready signal, and
time-out counter are checked to see if a Host interrupt needs to be sent. The data ready signal will be activated
and MMM sits poised to accept another data word.
We highly recommend the host should read the MMM IIR register to determine the type of interrupt. Then it might
check bit 7 of the LSR to see if there are any errors in the data currently residing in the receive FIFO. Finally, it
will (1) alternately read a data word through the RX FIFO read pointer and the error bits via the MMM LSR until
the FIFO is empty, or (2) read successive data words (knowing there were no errors in the FIFO) until the trigger
count is met.
A similar sequence occurs when data flows in the other direction (from host through transmit FIFO), except there
is no error bit manipulation/checking involved.