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Texas Instruments 4Q 2006 Interface Selection Guide
Design Considerations
PCI Express
®
takes the best features and
ideas behind PCI and combines them with
more than 10 years of industry “lessons
learned.” The result is a robust, scalable,
flexible, cost-effective I/O interconnect that
will serve the industry for the next 10-15 years.
Key Features
• PCI Express architecture is an industry
standard high-performance, general-
purpose serial I/O interconnect designed
for use in enterprise, desktop, mobile,
communications and embedded platforms.
• It is PCI-compatible by using the estab-
lished PCI software programming models.
PCI Express facilitates a smooth transition
to new hardware and allows software to
evolve and leverage the advantages of
PCI Express features.
• Gen I has a scalable bandwidth of 16
Gigabytes-per-second at its initial signal-
ing rate of 2.5GHz. In the future, Gen II
promises much higher transfer rates using
higher frequency signaling technologies.
• Supports multiple interconnect widths via
1, 2, 4, 8, 12, 16 and 32 lane configura-
tions aggregated to match application
bandwidth needs.
• Serves new and innovative, hot-plug/
hot-swap add-in card and module devices.
• Delivers unique, advanced features such
as Power Management, Quality of Service
and other native functions not available in
other I/O architectures.
Device A Device C
Device BDevice
PCI Express
®
Reference ClockReference Clock
Device B
PCI Express
PCI Express
PCI/PCI-X
PCI
Express
PCI
Express
PCI
Express
PCI
Express
Legacy
Endpoint
Legacy
Endpoint
PCI Express
Endpoint
PCI Express
Endpoint
PCI Express-PCI
Bridge
PCI Express
Memory
PCI Express
Endpoint
CPU
Root
Complex
Switch
PCI Express
Bridge
XIO2000A XIO3130 XIO2200A XIO1100
PCI Express
Switch
PCI Express
Portfolio
PCI Express
Endpoint
PCI Express
PHY
Device
Classifications
• Root Complex
• Switch
• PCI/PCI-X
• Bridge
• Legacy Endpoint
• Endpoint
PCI Express
®
topology.
Current TI PCI Express
®
portfolio.
PCI Express
®
29
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