Filter
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Schematic
1-3
Hardware
1.2 Schematic
Figure 1–2. Schematic Diagram
DTC
COMP
R9
RT
OUT
SCP
GND
V
CC
6
3
4
7
R9
1
5
FB
+
C1
µ1F
R2
C3
0.0022
µF
C2
0.033
µF
R8
C9 0.22
µF
C15
µ1.0 F
R6
2
8
U1
TL5001
1IN
2OUT
GND
V
CC
2
4
5
7
2IN
3
1OUT
V
DD
REG
8
61
R10
R13
IRF7201
NMOS
Q2
U2
TPS2812
C14
0.1 µ F
CR3
BAS16ZX
C11
0.47 µF
C5
100 µ F
C10
100 µ F
+
2
3
4
1
J1
I
V
GND
2
3
4
1
J2
5.5 V to 12 V
Q1
IRF7406
PMOS
C4
µ0.022 F
R3
R4
CR1
30BQ015
R7
C6
1000 pF
L1
27
µH
C12
100 µF
+
C7
100
+
C13
10 µFµ F
3.3 V
RTN
+
GND
I
V
3.3 V
RTN
CR2
BAS16ZX
15 Ω
121 kΩ
R12 10 kΩ
R11 30 kΩ
90.9 kΩ
1.00 kΩ
1.6 kΩ
R5
10 kΩ
10 kΩ
2.32 kΩ
180 Ω
3.3 Ω
1 kΩ
Note: Frequency is set to 100 kHz by R9. See TL5001 data sheet for the curve of oscillator frequency versus timing resistance.