Filter
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Design Procedures
2-8
Figure 2–2. Compensation Network
_
+
C4
R3
R4
C3
C2
R2
V
ref
V
O
V
I
The transfer function for this circuit is:
V
O
V
I
[1 sR2(C2 C3)] [1 sC4(R3 R4)]
sC2R4 [1 sC3R2][1 sC4R3]
f
Z1
f
Z2
f
P1
f
P2
f
P3
The desired output regulation is ±6 percent total deviation. The PWM control-
ler tolerance is ±5 percent, and the divider resistors are 1 percent; therefore,
the control loop must be very precise. A minimum dc gain of 1000 (60 dB) gives
a 0.1 percent tolerance. The integrator (R4, C2) sets the gain of the compensa-
tion network. The minimum modulator gain is 18 dB, therefore the compensa-
tion network must have a gain of at least 42 dB. With a desired crossover fre-
quency of 20 kHz and a desired slope of 20 dB per decade, choose an integra-
tor frequency of 2 kHz. This gives a gain of 46 dB at 10 Hz, which is sufficient
for this application. If more gain is needed, increase the integrator frequency.
R4 is already known, so C2 is calculated as:.
C2
1
2
f
P1
(R4)
1
2 (2 kHz)(2.32 k )
0.034 F 0.033 F
Setting f
Z2
= 3 kHz to compensate for one of the LC poles gives:
C4
1
2
f
Z2
(R4)
1
2 (3 kHz)(2.32 k )
0.023 F 0.022 F
Now R3 can be calculated using f
P3
(40 kHz), the ESR compensator:
R3
1
2
f
P3
(C4)
1
2 (40 kHz)(0.022 F)
181 180
The other LC filter compensator uses R2 and C2:
R2
1
2
f
Z1
(C2)
1
2 (3 kHz)(0.033 F)
1.6 k
The final rolloff pole (selected at 50 kHz) uses C3 and R2:
C3
1
2
f
P2
(R2)
1
2 (50 kHz)(1.6 k )
0.002 F 0.0022 F