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EMACFunctionalArchitecture
Table5summarizestheindividualEMACandMDIOsignalsfortheRGMIIinterface.
Table5.EMACandMDIOSignalsforRGMIIInterface
SignalNameI/ODescription
TXCOTransmitclock(TXC).Thetransmitclockisacontinuousclockthatprovidesthetiming
referencefortransmitoperations.TheTXDandTXCTLsignalsaretiedtothisclock.The
clockisdrivenbytheEMACandis2.5MHzat10Mbpsoperation,25MHzat100Mbps
operation,and125MHzat1000Mbpsoperation.
TXD[3-0]OTransmitdata(TXD).Thetransmitdatapinsareacollectionof4datasignalscomprising4
bitsofdata.TDX0istheleast-significantbit(LSB).ThesignalsaresynchronizedbyTXCand
validonlywhenTXCTLisasserted.Thelower4bitsofdataaretransmittedontherising
edgeoftheclock,andthehigher4bitsofdataaretransmittedonthefallingedgeoftheTXC.
TXCTLOTransmitenable(TXCTL).ThetransmitenablesignalindicatesthattheTXDpinsare
generatingnibbledataforusebythePHY.ItisdrivensynchronouslytoTXC.
REFCLKOReferenceclock(REFCLK).This125MHzreferenceclockisprovidedasaconvenience.It
canbeusedasaclocksourcetothePHY,sothatthePHYmaygeneratetheRXCclockto
besenttoEMAC.Thisclockisstoppedwhilethedeviceisinreset.
RXCIReceiveclock(RXC).Thereceiveclockisacontinuousclockthatprovidesthetiming
referenceforreceiveoperations.TheRXD,andRXCTLsignalsaretiedtothisclock.The
clockisgeneratedbythePHYandis2.5MHzat10Mbpsoperation,25MHzat100Mbps
operation,and125MHzat1000Mbpsoperation.
RXD[3-0]IReceivedata(RXD).Thereceivedatapinsareacollectionof4datasignalscomprising4bits
ofdata.RDX0istheleast-significantbit(LSB).ThesignalsaresynchronizedbyRXCand
validonlywhenRXCTLisasserted.Thelower4bitsofdataarereceivedontherisingedge
oftheclock,andthehigher4bitsofdataarereceivedonthefallingedgeoftheRXC.
RXCTLIReceivecontrol(RXCTL).Thereceivecontroldatahasthereceivedatavalid(MRXDV)
signalontherisingedgeofthereceiveclock,andaderivativeofreceivedatavalidand
receiveerror(MRXER)onthefallingedgeofRXC.
Whenreceivingavalidframewithnoerrors,MRXDV=TRUEisgeneratedasalogichighon
therisingedgeonRXCandMRXER=FALSEisgeneratedasalogichighonthefalling
edgeofRXC.
Whennoframeisbeingreceived,MRXDV=FALSEisgeneratedasalogiclowontherising
edgeofRXCandMRXER=FALSEisgeneratedasalogiclowonthefallingedgeofRXC.
Whenreceivingavalidframewitherrors,MRXDV=TRUEisgeneratedasalogichighon
therisingedgeofRXCandMRXER=TRUEisgeneratedasalogiclowonthefallingedge
ofRXC.
MDCLKOManagementdataclock(MDCLK).TheMDIOdataclockissourcedbytheMDIOmodule.It
synchronizesMDIOdataaccessoperationsdoneontheMDIOpin.Thefrequencyofthis
clockiscontrolledbytheCLKDIVbitsintheMDIOcontrolregister(CONTROL).
MDIOI/OManagementdatainputoutput(MDIO).TheMDIOpindrivesPHYmanagementdataintoand
outofthePHYbywayofanaccessframeconsistingofstartofframe,read/writeindication,
PHYaddress,registeraddress,anddatabitcycles.TheMDIOpinactsasanoutputfor
everythingexceptthedatabitcycles,whenthepinactsasaninputforreadoperations.
SPRU975B–August2006EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)23
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