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2.13TransferNodePriority
2.14ResetConsiderations
2.14.1SoftwareResetConsiderations
2.14.2HardwareResetConsiderations
EMACFunctionalArchitecture
Latencytosystem’sinternalandexternalRAMcanbecontrolledthroughtheuseofthetransfernode
priorityallocationregisterintheC645xdevices.LatencytodescriptorRAMislowbecauseRAMislocalto
theEMAC,asitispartoftheEMACcontrolmodule.
TheC645xdevicescontainasystemlevelpriorityallocationregister(PRI_ALLOC)thatsetsthepriorityof
thetransfernodeusedinissuingmemorytransferrequeststosystemmemory.
AlthoughtheEMAChasinternalFIFOstohelpalleviatememorytransferarbitrationproblems,theaverage
transferrateofdatareadandwrittenbytheEMACtointernalorexternalDSPmemorymustbeatleast
equaltotheEthernetwirerate.Inaddition,theinternalFIFOsystemcannotwithstandasinglememory
latencyeventgreaterthanthetimeittakestofilloremptyaTXCELLTHRESHnumberofinternal64-byte
FIFOcells.
Forexample,for1000Mbpsoperation,theserestrictionstranslateintothefollowingrules:
•Fortheshort-termaverage,each64-bytememoryread/writerequestfromtheEMACmustbeserviced
innomorethan0.512µs.
•Anysinglelatencyeventinrequestservicingcanbenolongerthan(0.512*TXCELLTHRESH)µs.
Bits[0-2]ofthePRI_ALLOCregistersetthetransfernodepriorityforallthemasterperipheralsinthe
device,includingEMAC.Avalueof000bwillhavethehighestpriority,while111bwillhavethelowest.
ThedefaultpriorityassignedtoEMACis001b.Itisimportanttohaveabalancebetweenallperipherals.
Inmostcases,thedefaultprioritieswillnotneedadjustment.
Forinformationonthechiplevelresetcapabilitiesofvariousperipherals,seethedevice-specificdata
manual.
Withintheperipheralitself,theEMACcomponentoftheEthernetMACperipheralcanbeplacedinareset
statebywritingtotheSOFTRESETregisterlocatedinEMACmemorymap.Writingaonetobit0ofthis
registercausestheEMAClogictobereset,andtheregistervaluestobesettotheirdefaultvalues.
SoftwareresetoccurswhenthereceiveandtransmitDMAcontrollersareinanidlestatetoavoidlocking
uptheconfigurationbus;itistheresponsibilityofthesoftwaretoverifythattherearenopendingframesto
betransferred.Afterwritingaonetothisbit,itmaybepolledtodetermineiftheresethasoccurred.A
valueofoneindicatesthattheresethasnotyetoccurred.Avalueofzeroindicatesthataresethas
occurred.
Afterasoftwareresetoperation,alltheEMACregistersneedtobere-initializedforproperdata
transmission.
UnliketheEMACmodule,theMDIOandEMACcontrolmodulescannotbeplacedinresetfromaregister
insidetheirmemorymap.
Whenahardwareresetoccurs,theEMACperipheralwillhaveitsregistervaluesreset,andallthe
sub-moduleswillreturntotheirdefaultstate.Afterthehardwarereset,theEMACneedstobeinitialized
beforeresumingitsdatatransmission,asdescribedinSection2.15.
Ahardwareresetistheonlymeansofrecoveringfromtheerrorinterrupts(HOSTPEND),whichare
triggeredbyerrorsinpacketbufferdescriptors.Beforedoingahardwarereset,youshouldinspectthe
errorcodesintheMACSTATUSregister.Thisregisterprovidesinformationaboutthesoftwareerrortype
thatneedscorrection.Formoreinformationonerrorinterrupts,seeSection2.16.1.4.
EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO) 56SPRU975B–August2006
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