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Satellite T110D and Satellite Pro T110D Tests and Diagnostics Manual 19
5. Address pattern test
“16 bit write and 16 bit read” of address pattern data is executed and
the new data is compared with the original data.
Test data = 0000H, 0004H, 0008H, 000CH,...8000H, 8004H, through
FFECH
Subtest 02 Protected Mode
This subtest first writes data patterns and address data from 1 to 32 MB, then
reads the new data and compares the result with the original data patterns.
Addresses are displayed in 64KB increments during the test.
. Test Process:
1. Byte Enable Test
One bit write/ 8 bit read” is executed and the new data is compared
with the original data.
Test data = CCAA5533H, 80000000H
2. Byte Enable Test
“One bit write/16 bit read” is executed and the new data is compared
with the original data.
Test data = CCAA5533H, 80000000H
3. Data bus test
“One bit write/16 bit read” is executed and the new data is compared
with the original data.
Test data = 1H, 2H, 4H, 8H, 10H, through 80000000H.
4. Fixed data test
“16 bit write/ 16 bit read” is executed and the new data is compared
to the original data.
Test data = FFFFFFFFH, 00000000H, 80018001H
5. Address pattern test
“16 bit write and 16 bit read” of address pattern data is executed and
the new data is compared with the original data.
Test data = 0000H, 0004H, 0008H, 000CH,...8000H, 8004H, through
FFECH
Subtest 03 Protected Mode [32MB - MAX]
This subtest first writes data patterns and address data from 32MB to the
maximum installed memory, reads the new data, and then compares the result