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Advanced Chipsets Features
This section describes advanced chipset features.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
This option permits you to either manually select memory tim-
ings, or allow the SPD (Serial Presence Detect) to determine
the said timings automatically. The choices are:
Manual / By SPD
Note: On all memory timing settings, a
lower number is more aggressive.
CAS Latency Time
This setting controls the time delay (in clock cycles - CLKs)
that passes before the DRAM starts to carry out a read com-
mand after receiving it. This also determines the number of
CLKs for the completion of the first part of a burst transfer. In
other words, the lower the latency, the faster the transaction.
The possible values are:
2 / 2.5 / 3
DRAM Timing Selectable
CAS Latency Time
Active to Precharge Delay
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
System BIOS Cacheable
Video BIOS Cacheable
Delay Prior to Thermal
DRAM Data Integrity Mode
[By SPD]
[2]
[8]
[4]
[4]
[Enabled]
[Disabled]
[16 Min]
[ECC]
Item Help
______________________
Menu Level X
↑↓←→: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults