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P a g e 16
PMC4U_STAT
[0X04] PMC-4U Status Port read only
STATUS
DATA BIT DESCRIPTION
31-2 spare
1 interrupt out
0 interrupt status
FIGURE 5 PMC-4U TX CONTROL REGISTER BIT MAP
Interrupt out indicates that an interrupt is asserted on the PCI bus.
Interrupt status indicates that an interrupt condition exists, however if the
master interrupt enable is not asserted, then the interrupt will not be
asserted on the PCI bus. This bit can be used to operate the card in polled
mode without interrupting the host.
PMC4U_MSK
[0X08] PMC-4U Interrupt Mask Register Port read/write
INTERRUPT MASK
DATA BIT DESCRIPTION
31-5 Spare
4 SCC Interrupt Enable
3 UART D Interrupt Enable
2 UART C Interrupt Enable
1 UART B Interrupt Enable
0 UART A Interrupt Enable
FIGURE 6 PMC-4U INTERRUPT MASK REGISTER BIT MAP
The bits in this register enable the individual interrupts from the devices
indicated. The mask bit for a device must be set to a one in order for an
interrupt from that device to affect the PMC-4U interrupt status.