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SDRAM Interface
1-8 ADSP-BF538F EZ-KIT Lite Evaluation System Manual
SDRAM Interface
The three SDRAM control registers must be initialized in order to use the
MT48LC32M8A2 32M x 16 bits (64 MB) SDRAM memory. When you
are in a VisualDSP++ session and connect to the EZ-KIT Lite board, the
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start Address End Address Content
External
Memory
0x0000 0000 0x03FF FFFF SDRAM bank 0 (SDRAM). See “SDRAM Inter-
face” on page 1-8.
0x2000 0000 0x200F FFFF ASYNC memory bank 0. See “Flash Memory” on
page 1-10.
0x2010 0000 0x201F FFFF ASYNC memory bank 1. See “Flash Memory” on
page 1-10.
0x2020 0000 0x202F FFFF ASYNC memory bank 2. See “Flash Memory” on
page 1-10.
0x2030 0000 0x203F FFFF ASYNC memory bank 3. See “Flash Memory” on
page 1-10.
All other locations Not used
Internal
Memory
0xFF80 0000 0xFF80 3FFF Data bank A SRAM 16 KB
0xFF80 4000 0xFF80 7FFF Data bank A SRAM/CACHE 16 KB
0xFF90 0000 0xFF90 7FFF Data bank B SRAM 16 KB
0xFF90 4000 0xFF90 7FFF Data bank B SRAM/CACHE 16 KB
0xFFA0 0000 0xFFA0 7FFF Instruction bank A SRAM 32 KB
0xFFA1 0000 0xFFA1 3FFF Instruction bank B SRAM 16 KB
0xFFA0 8000 0xFFA0 BFFF Instruction SRAM/CACHE 16 KB
0xFFB0 0000 0xFFB0 0FFF Scratch pad SRAM 4 KB
0xFFC0 0000 0xFFDF FFFF System MMRs 2 MB
0xFFE0 0000 0xFFFF FFFF Core MMRs 2 MB
All other locations Reserved