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ADSST-SALEM-3T
Rev. 0 | Page 6 of 24
ADSST-218X COMMON-MODE PINS
Table 2.
Pin Name No. of Pins I/O Function
BG
1 O Bus Grant Output
BGH
1 O Bus Grant Hung Output
BMS
1 O Byte Memory Select Output
BR
1 I Bus Request Input
CMS
1 O Combined Memory Select Output
DMS
1 O Data Memory Select Output
IOMS
1 O Memory Select Output
PMS
1 O Program Memory Select Output
RD
1 O Memory Read Enable Output
RESET
1 I Processor Reset Input
WR
1 O Memory Write Enable Output
IRQ2/
1 I Edge- or Level-Sensitive Interrupt Request
1
PF7 I/O Programmable I/O Pin
IRQL1/
1 I Level-Sensitive Interrupt Requests
1
PF6 I/O Programmable I/O Pin
IRQL0/
1 I Level-Sensitive Interrupt Requests
1
PF5 I/O Programmable I/O Pin
IRQE/
1 I Edge-Sensitive Interrupt Requests
1
PF4 I/O Programmable I/O Pin
MODE A 1 I
Mode Select Input−Checked only during RESET
PF0 I/O Programmable I/O Pin during Normal Operation
MODE B 1 I
Mode Select Input−Checked only during RESET
PF1 I/O Programmable I/O Pin during Normal Operation
MODE C 1 I
Mode Select Input−Checked only during RESET
PF2 I/O Programmable I/O Pin during Normal Operation
MODE D 1 I
Mode Select Input−Checked only during RESET
PF3 I/O Programmable I/O Pin during Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
EZ-Port 9 I/O For Emulation Use
FI, FO Flag In, Flag Out
2
FL0, FL1, FL2 3 O Output Flags
GND 10 I Power and Ground
IRQ1:0
Edge- or Level-Sensitive Interrupts
PWD
1 I Power-Down Control Input
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
PWDACK 1 O Power-Down Control Output
V
DDEXT
4
I External V
DD
(2.5 V or 3.3 V) Power (LQFP)
V
DDEXT
7
I External V
DD
(2.5 V or 3.3 V) Power (Mini-BGA)
V
DDINT
2 I Internal V
DD
(2.5 V) Power (LQFP)
V
DDINT
4 I Internal V
DD
(2.5 V) Power (Mini-BGA)
1
Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control register. Software configurable.