Asus P5P800S Computer Hardware User Manual


 
ASUS P5P800SASUS P5P800S
ASUS P5P800SASUS P5P800S
ASUS P5P800S
1-151-15
1-151-15
1-15
1.7 System memory
1.7.11.7.1
1.7.11.7.1
1.7.1
OverviewOverview
OverviewOverview
Overview
The motherboard comes with two 184-pin Double Data Rate (DDR) Dual
Inline Memory Modules (DIMM) sockets. The following figure illustrates the
location of the sockets:
1.7.21.7.2
1.7.21.7.2
1.7.2
Memory ConfigurationsMemory Configurations
Memory ConfigurationsMemory Configurations
Memory Configurations
You may install 128 MB, 256 MB, 512 MB and 1 GB unbuffered non-ECC
DDR DIMMs into the DIMM sockets using the memory configurations in this
section.
P5P800S
®
P5P800S 184-pin DDR DIMM sockets
DIMM1
DIMM2
1. For optimum compatibility, it is recommended that you obtain
memory modules from the same vendor. See the DDR400 Qualified
Vendor List (QVL) on page 1-16.
2. Make sure that the memory frequency matches the CPU FSB (Front
Side Bus). Refer to the
Memory frequency/CPU FSBMemory frequency/CPU FSB
Memory frequency/CPU FSBMemory frequency/CPU FSB
Memory frequency/CPU FSB
synchronizationsynchronization
synchronizationsynchronization
synchronization table below.
3. Always install DIMMs with the same CAS Latency.
4. Double-sided DDR DIMMs with
x16x16
x16x16
x16 (data bus=16bit) memory chips
are not supported due to chipset limitation.
Memory frequency/CPU FSB synchronizationMemory frequency/CPU FSB synchronization
Memory frequency/CPU FSB synchronizationMemory frequency/CPU FSB synchronization
Memory frequency/CPU FSB synchronization
This motherboard supports different memory frequencies depending on the
CPU FSB (Front Side Bus) and the type of DDR DIMM.
CPU FSBCPU FSB
CPU FSBCPU FSB
CPU FSB
DDR DIMM TypeDDR DIMM Type
DDR DIMM TypeDDR DIMM Type
DDR DIMM Type
Memory FrequencyMemory Frequency
Memory FrequencyMemory Frequency
Memory Frequency
800 MHz PC3200/PC2700/PC2100 400/320*/266 MHz
533 MHz PC2700/PC2100 333/266 MHz
*When using 800 MHz FSB CPU, PC2700 DDR DIMMs run only at 320MHz
(not 333MHz) due to chipset limitation.