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Chapter 4: BIOS setupChapter 4: BIOS setup
Chapter 4: BIOS setupChapter 4: BIOS setup
Chapter 4: BIOS setup
Configure DRAM Timing by SPD [Enabled]Configure DRAM Timing by SPD [Enabled]
Configure DRAM Timing by SPD [Enabled]Configure DRAM Timing by SPD [Enabled]
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available. Configuration options: [6 Clocks]
[5 Clocks] [4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and the
read/write command. Configuration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [4 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Configuration options: [2 Clocks] ~ [6 Clocks]
DRAM ECC Mode [Auto]DRAM ECC Mode [Auto]
DRAM ECC Mode [Auto]DRAM ECC Mode [Auto]
DRAM ECC Mode [Auto]
Allows you to disable or set to [Auto] the DRAM ECC mode.
Configuration options: [Disabled] [Auto]
4.4.54.4.5
4.4.54.4.5
4.4.5
ChipsetChipset
ChipsetChipset
Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
DRAM ECC Mode [Auto]
Hyper Path 3 [Auto]
Booting Graphic Adapter Priori [PCI Express/PCI]
PEG Buffer Length [Auto]
Link Latency [Auto]
PEG Root Control [Auto]
PEG Link Mode [Auto]
Slot Power [Auto]
High Priority Port Select [Disabled]
Second PCI-E slot mode [Auto]