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II-10
90 µsec
STROBE
BUSY
ACK
STROBE
BUSY
ACK
0.5 µsec
0.5 µsec1.5 µsec
CPU Receive Mode
DMA Receive Mode
BUSY goes HIGH at the falling edge of STROBE. The data (8 bits) from the PC is
latched in the data buffer at the rising edge of STROBE. The pulse width of ACK
differs according to the speed MODE as shown above. BUSY goes LOW at the
rising edge of ACK.
<IEEE1284 support>
This supports the IEEE1284 data transfer with the following modes.
Nibble mode
Byte mode
(8) Data expansion
This circuit expands the compressed image data received from the PC, and writes
the bit map data to the FIFO.
(9) Software support
Supports 16 x 16 rotation, bit expansion, and bit search.
(10) EEPROM I/O
One output port and one I/O port are assigned.