Filter
Top Products
II-13
90 µsec
STROBE
BUSY
ACK
STROBE
BUSY
ACK
0.5 µsec
0.5 µsec1.5 µsec
CPU Receive Mode
DMA Receive Mode
BUSY goes HIGH at the falling edge of the STROBE signal. The data (8 bits) from
the PC is latched into the data buffer at the rising edge of the STROBE signal. The
pulse width of ACK varies according to the speed MODE as shown above. BUSY
goes LOW on the rising edge of ACK.
<IEEE1284 support>
This supports the IEEE1284 data transfer with the following mode.
Nibble mode
Byte mode
ECP mode
(8) Data expansion
This circuit expands the compressed image data received from the PC, and writes
the bit map data to the FIFO.
(9) Software support
Supports 16 x 16 rotation, bit expansion, bit search, and decimal point conversion.
(10) EEPROM I/O
One output port and one I/O port are assigned.