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Appendix
COM-2(PC)F58
LSI Recovery Time
Due to the ever higher CPU clock rates used in PCs, restrictions
apply when controlling a peripheral LSI device by software.
Table 6.8. lists the LSIs used on CONTEC boards which require
special consideration when accessing. Take note of the following
point when accessing these LSIs.
In PCs using i386 or earlier CPUs, software waits (JMP $+2) can be
used to provide a recovery time when accessing the LSI. However,
software waits cannot be used to provide a recovery time in PCs
with a i486 or later CPU because of the CPU cache memory
function.
The following describes one method of providing the recovery time
when using an i486 or later CPU.
In the PC/AT and compatible computers, executing an IN
instruction for the port at I/O address 2EFh (COM4 scratch register)
takes a minimum of 0.5µs. As this time does not depend on the
CPU type or clock rate, the time can be used to provide the
recovery time. After accessing any of the devices listed in
Table 6.8., execute the IN instruction for the 2EFh port the required
number of times to provide the recovery time.
Table 6.8. Number of Times the IN Instruction Must be
Executed for the 2EFh Port after Accessing the LSI
LSI Device Output Input
i8237 or equivalent None None
i8254 or equivalent Once Once
i8255 or equivalent Once Once
i8259 or equivalent Once Once
NS16550 or equivalent Once Once
µ
PD7210C Once None