Filter
Top Products
Appendix
COM-2(PC)F60
Various Aspects of Interrupt Handling in Enhanced Mode
and Compatible Mode
Enhanced Mode
When in Enhanced mode, two channels of the COM-2(PC)F share
the same interrupt request line. The interrupt levels can be set
from IRQ3~IRQ7, IRQ9~IRQ12, IRQ14, and IRQ15 by setting JP1
before installing this board. Each channel's interrupt signal will be
latched in the Interrupt Vector Register (IVR).
Therefore, when the CPU receives an interrupt requirement, the
interrupt service routine can check the IVR to determine which
channel is requesting interrupt service. After finishing the
interrupt service process, the interrupt service routine has to check
IVR again to see if a Pending interrupt request has occurred.
ACE (Asynchronous Communication Element) has its own internal
register for enabling interrupts and identifying the interrupt service
requesting channel. Refer to National Semiconductor's data book
for additional details on NS16550 and its operation.
When turning on the PC's main power, the ACE's master reset
function sets OUT1 to "High". This status automatically enables
the interrupt. If one of the two channels is not allowed to generate
the interrupt, set the OUT1 bit to "Low".
In addition to being able to enable/disable interrupt by channel, the
board also has a global interrupt enable function. This global
interrupt enable function determines whether the IRQ line is active
or not. When turning on the power, this function sets to the
disable status. To enable the PC bus to accept an interrupt, this
function has to be programmed to enable status. To enable this
function, write "1" to IVR's D7 bit; to disable this function, write
"0" to IVR's D7 bit.
Figure 6.14. describes the bit function of IVR in Enhanced mode.
The I/O address of IVR is either 2BF or 1BF.