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CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B Page 12 of 37
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOX
t
TDOV
Switching Waveforms
Master Reset
[10]
Notes:
10.t
S
is the set-up time required for all input control signals.
11.To Reset the test port without resetting the device, TMS must be held low for five clock cycles.
MRST
t
RSR
t
RS
INACTIVE
ACTIVE
TDO
INT
CNTINT
t
RSF
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
t
CH2
t
CL2
t
CYC2
CLK
t
S
TMS
[11]
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