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CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 25 of 51
13.0 I
2
C-compatible Controller
The I
2
C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-
master modes of operation. The I
2
C-compatible block functions by handling the low-level signaling in hardware, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I
2
C-compatible bus idle if necessary.
The I
2
C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 16.8.
The I
2
C-compatible interface consists of two registers, an I
2
C Data Register (Figure 13-1) and an I
2
C Status and Control Register
(Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I
2
C Status and Control
Register should only be monitored after the I
2
C interrupt, as all bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
The I
2
C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I
2
C SDA data is connected to bit 1 of GPIO port
1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I
2
C Configuration Register, which is
used to set the locations of the configurable I
2
C-compatible pins. Once the I
2
C-compatible functionality is enabled by setting bit
0 of the I
2
C Status & Control Register, the two LSB bits ([1:0]) of the corresponding GPIO port are placed in Open Drain mode,
regardless of the settings of the GPIO Configuration Register.The electrical characteristics of the I
2
C-compatible interface is the
same as that of GPIO ports 1 and 2. Note that the I
OL
(max) is 2 mA @ V
OL
= 2.0 V for ports 1 and 2.
All control of the I
2
C clock and data lines is performed by the I
2
C-compatible block.
I
2
C Data ADDRESS 0x29
Bits [7..0] : I
2
C Data
Contains the 8 bit data on the I
2
C Bus
I
2
C Status and Control
The I
2
C Status and Control register bits are defined in Table 14-1, with a more detailed description following.
Table 12-1. HAPI Port Configuration
Port Width (Bits[1:0]) HAPI Port Width
11 24 Bits: P3[7:0], P1[7:0], P0[7:0]
10 16 Bits: P1[7:0], P0[7:0]
01 8 Bits: P0[7:0]
00 No HAPI Interface
Table 12-2. I
2
C Port Configuration
I
2
C Position (Bit[7]) Port Width (Bit[1]) I
2
C Position
X1I
2
C on P2[1:0], 0:SCL, 1:SDA
00I
2
C on P1[1:0], 0:SCL, 1:SDA
10I
2
C on P2[1:0], 0:SCL, 1:SDA
Bit # 76543210
Bit Name I
2
C Data 7 I
2
C Data 6 I
2
C Data 5 I
2
C Data 4 I
2
C Data 3 I
2
C Data 2 I
2
C Data 1 I
2
C Data 0
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Reset XXXXXXXX
Figure 13-1. I
2
C Data Register
Bit # 76543210
Bit Name MSTR Mode Continue/Busy Xmit Mode ACK Addr ARB
Lost/Restart
Received Stop I
2
C Enable
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Reset 00000000
Figure 13-2. I
2
C Status and Control Register
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