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PowerEdge T110 II Technical Guide 26
8 Chipset
8.1 Overview
The PowerEdge T110 II planar incorporates the Intel
®
C200 Series PCH chipset. The features listed
below are part of the chipset.
8.2 Direct Media Interface
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C200 series
chipset. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
8.3 PCI Express Interface
The C200 series chipset provides up to 8 PCI Express root ports, supporting bandwidths of 2.5 GT/s
and 5 GT/s. PCI Express Root Ports 1-4 can be statically configured as four x1 ports or ganged
together to form one x4 port. Ports 5 and 6 can only be used as two x1 ports.
8.4 SATA interface:
The chipset supports up to six Serial ATA (SATA) ports capable of independent DMA operation. The
SATA controllers are completely software transparent with an IDE interface, providing a lower pin
count and higher performance. PCH SATA interface supports data transfer rates up to 3 Gb/s (300
MB/s) per port. The SATA controller contains two modes of operation— a legacy mode using I/O
space and an AHCI mode using memory space.
The chipset supports the Serial ATA Specification, Revision 3.0. Additionally, the chipset is capable
of supporting data transfer rates up to 3 Gb/s (300 MB/s) external SATA (eSATA) to ease the addition
of external high performance storage devices.
8.5 AHCI:
The C200 series chipset provides hardware support for Advanced Host Controller Interface (AHCI), a
new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage
of performance features, such as having no master/slave designation for SATA devices—each device
is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability
enhancements such as hot-plugging. AHCI requires appropriate software support (an AHCI driver) and
for some features, it requires hardware support in the SATA device or additional platform hardware.
8.6 PCI Interface:
The chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. It integrates a PCI arbiter
that supports up to four external PCI bus masters in addition to the internal chipset requests. This
allows for combinations of up to four PCI down devices and PCI slots.
8.7 Low Pin Count (LPC) Interface:
The C200 series chipset implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the chipset resides in PCI Device 31: Function 0. In addition to
the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt
controllers, timers, power management, system management, GPIO, and RTC.