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PowerEdge T110 II Technical Guide 27
8.8 Serial Peripheral Interface (SPI):
The chipset implements an SPI Interface as an alternative interface for the BIOS flash device. The
chipset supports up to two SPI flash devices with speeds up to 20 MHz, 33 MHz utilizing two chip
select pins.
8.9 Compatibility Module
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently
programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels
5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be
programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request.
The chipset supports LPC DMA, which is similar to ISA DMA, through the DMA controller. LPC DMA is
handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from
the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the system
timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for
these three counters.
The chipset provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates
the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so
that 14 external and two internal interrupts are possible. In addition, the chipset supports a serial
interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save and restore
system state after power has been removed and restored to the platform.
8.10 Advanced Programmable Interrupt Controller (APIC):
In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in the
previous section, the chipset incorporates the Advanced Programmable Interrupt Controller (APIC).
8.11 USB interface:
The C200 series Essential supports twelve USB 2.0 ports that support high-speed, full-speed, and low-
speed USB devices. The PCH has two EHCI Host Controllers: EHCI#1 with 8 ports, and EHCI#2 with 6
ports. Each EHCI has an integrated USB 2.0 Rate Matching Hub (RMH). The RMHs replace the
functionality of the UHCI controllers by converting high-speed traffic into low- and full-speed traffic.
When the RMHs are enabled the UHCI controllers are disabled.
8.12 RTC:
The chipset contains a Motorola MC146818A-compatible real-time clock with 256 bytes of battery-
backed RAM.
The real-time clock performs two key functions: keeping track of the time of day and storing system
data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V
battery.
The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-
byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in
advance, rather than only 24 hours in advance.