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PowerEdge T110 II Technical Guide 28
8.13 GPIO:
Various general purpose inputs and outputs are provided for custom system design. The number of
inputs and outputs varies depending on C200 series configuration.
8.14 Enhanced Power Management
The C200 series power management functions include enhanced clock control and various low-power
(suspend) states (for example, Suspend-to-RAM and Suspend-to-Disk). A hardware-based thermal
management circuit permits software-independent entrance to low-power states. The chipset
contains full support for the Advanced Configuration and Power Interface (ACPI) Specification,
Revision 3.0a.
8.15 System Management Features
The C200 series chipset integrates several functions designed to manage the system and lower the
total cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an external
microcontroller.
8.15.1 TCO Timer
The chipset‘s integrated programmable TCO timer is used to detect system locks. The first expiration
of the timer generates an SMI# that the system can use to recover from a software lock. The second
expiration of the timer causes a system reset to recover from a hardware lock.
8.15.2 Processor Present Indicator
The chipset looks for the processor to fetch the first instruction after reset. If the processor does not
fetch the first instruction, the chipset will reboot the system.
8.15.3 Error Code Correction (ECC) Reporting
When detecting an ECC error, the host controller has the ability to send one of several messages to
the chipset. The host controller can instruct the chipset to generate an SMI#, NMI, SERR#, or TCO
interrupt.
8.15.4 Function Disable
The chipset provides the ability to disable the following integrated functions: LAN, USB, LPC, Intel
HD Audio, SATA, PCI Express or SMBus. Once disabled, these functions no longer decode I/O,
memory, or PCI configuration space. Also, no interrupts or power management events are generated
from the disabled functions.
8.16 System Management Bus (SMBus 2.0)
The chipset contains an SMBus Host interface that allows the processor to communicate with SMBus
slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.
The chipset‘s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the chipset supports slave functionality,
including the Host Notify protocol. Hence, the host controller supports eight command protocols of
the SMBus interface: Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word,
Process Call, Block Read/Write, and Host Notify.