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30 NS9210 Processor Module Hardware Reference
Chapter 1
GPIO31 D15 TXDD Reserved Reserved for upper data
lines
GPIO32 MII_MDC PIC_0_GEN_IO[0] Reserved MII Interface
GPIO33 MII_TXC PIC_0_GEN_IO[1] Reserved MII Interface
GPIO34 MII_RXC PIC_0_GEN_IO[2] Reserved MII Interface
GPIO35 MII_MDIO PIC_0_GEN_IO[3] Reserved MII Interface
GPIO36 MII_RXDV PIC_0_GEN_IO[4] Reserved MII Interface
GPIO37 MII_RXER PIC_0_GEN_IO[5] Reserved MII Interface
GPIO38 MII_RXD0 PIC_0_GEN_IO[6] Reserved MII Interface
GPIO39 MII_RXD1 PIC_0_GEN_IO[7] Reserved MII Interface
GPIO40 MII_RXD2 PIC_1_GEN_IO[0] Reserved MII Interface
GPIO41 MII_RXD3 PIC_1_GEN_IO[1] Reserved MII Interface
GPIO42 MII_TXEN PIC_1_GEN_IO[2] Reserved MII Interface
GPIO43 MII_TXER PIC_1_GEN_IO[3] Reserved MII Interface
GPIO44 MII_TXD0 PIC_1_GEN_IO[4] Reserved MII Interface
GPIO45 MII_TXD1 PIC_1_GEN_IO[5] Reserved MII Interface
GPIO46 MII_TXD2 PIC_1_GEN_IO[6] Reserved MII Interface
GPIO47 MII_TXD3 PIC_1_GEN_IO[7] Reserved MII Interface
GPIO48 MII_COL Reserved Reserved MII Interface
GPIO49 MII_CRS Reserved Reserved MII Interface
GPIO50 MII_PHY_Int PIC_1_CLK (I) PIC_1_CLK(0) MII Interface
GPIO51 DCDB# (dup) PIC_0_BUS_1[8] PIC_1_BUS_1[8] DCDB#
GPIO52 CTSB# (dup) PIC_0_BUS_1[9] PIC_1_BUS_1[9] CTSB#
GPIO53 DSRB# (dup) PIC_0_BUS_1[10] PIC_1_BUS_1[10] DSRB#
GPIO54 RXDB (dup) PIC_0_BUS_1[11] PIC_1_BUS_1[11] RXDB
GPIO55 RIB# (dup) PIC_0_BUS_1[12] PIC_1_BUS_1[12] RIB#
GPIO56 RTSB# / 485CTLB
(dup)
PIC_0_BUS_1[13] PIC_1_BUS_1[13] RTSB#
GPIO57 TXCLKB (dup) /
DTRB# (dup)
PIC_0_BUS_1[14] PIC_1_BUS_1[14] DTRB#
GPIO58 TXDB (dup) PIC_0_BUS_1[15] PIC_1_BUS_1[15] TXDB
GPIO59 DCDD# (dup) PIC_0_BUS_1[16] PIC_1_BUS_1[16] DCDD#
GPIO60 CTSD# (dup) PIC_0_BUS_1[17] PIC_1_BUS_1[17] CTSD#
Port
name,
Function
03
Alternate function
00
Alternate function
01
Alternate
function 02
Alternate
function 04 (only
GPIO00...GPIO15)
On module, default
used as