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Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
48 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD Mn,A Load A-register into memory
LD Mn,A
M(n
3 to n0) ← A
11111000n
3 n2 n1 n0 F80H to F8FH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the A-register into the location addressed by Mn.
LD M0AH,A LD M0BH,A
A register 0110 0110 0110
Memory (0AH) 0100 0110 0110
Memory (0BH) 1011 1011 0110
LD Mn,B Load B-register into memory
LD Mn,B
M(n
3 to n0) ← B
11111001n
3 n2 n1 n0 F90H to F9FH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the B-register into the data memory location addressed by
Mn.
LD M0,B LD M1,B
B register 0100 0100 0100
Memory (00H) 1011 0100 0100
Memory (01H) 1111 1111 0100