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Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 59
3 INSTRUCTION SET
LD Y,e Load immediate data e into Y-register
LD Y,e
YH ← e
7 to e4, YL ← e3 to e0
1000e7 e6 e5 e4 e3 e2 e1 e0 800H to 8FFH
I
5
Not affected
Not affected
Not affected
Not affected
Loads 8-bit immediate data e into register Y.
LD Y,E1H
YH register 0001 1110
YL register 1100 0001
LD YH,r Load r-register into YH
LD YH,r
YH ← r
1110100101r1 r0 E94H to E97H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four high-order bits of register Y.
LD YH,B LD YH,MX
YH register 0000 0110 0101
B register 0110 0110 0110
Memory (MX) 0101 0101 0101