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Instruction List (3)
S1C6200 Core CPU
Opcode
CP
LD
LDPX
LDPY
LBPX
SET
RST
SCF
RCF
SZF
RZF
SDF
RDF
EI
DI
INC
DEC
PUSH
POP
Clasiffication
Index
operation
instructions
Data transfer
instructions
Flag
operation
instructions
Stack
operation
instructions
Operand
XH, i
XL, i
YH, i
YL, i
r, i
r, q
A, Mn
B, Mn
Mn, A
Mn, B
MX, i
r, q
MY, i
r, q
MX, l
F, i
F, i
SP
SP
r
XP
XH
XL
YP
YH
YL
F
r
Function
XH-i
XL-i
YH-i
YL-i
r←i
r←q
A←M(n)
B←M(n)
M(n)←A
M(n)←B
M(X)←i, X←X+1
r←q, X←X+1
M(Y)←i, Y←Y+1
r←q, Y←Y+1
M(X)←l[3:0], M(X+1)←l[7:4], X←X+2
F←F | i
F←F & i
C←1
C←0
Z←1
Z←0
D←1 (Decimal adjustment ON)
D←0 (Decimal adjustment OFF)
I←1 (Enable interrupt)
I←0 (Disable interrupt)
SP←SP+1
SP←SP-1
SP←SP-1, M(SP)←r
SP←SP-1, M(SP)←XP
SP←SP-1, M(SP)←XH
SP←SP-1, M(SP)←XL
SP←SP-1, M(SP)←YP
SP←SP-1, M(SP)←YH
SP←SP-1, M(SP)←YL
SP←SP-1, M(SP)←F
r←M(SP), SP←SP+1
Clk
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
↔
↔
↔
↔
–
–
–
–
–
–
–
–
–
–
–
1
0
–
–
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C
↔
↔
↔
↔
–
–
–
–
–
–
–
–
–
–
–
1
0
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
–
–
–
–
–
–
1
0
–
–
–
–
–
–
–
–
–
–
–
D
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
–
–
–
–
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
Code
MSB LSB
Mnemonic
Flags
Remarks
i
i
i
i
i
i
n
n
n
n
q
r
r
q
r
r
r
i
l
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q
r