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AN42 APPLICATION NOTE
20
4. Premature shut down can be caused by an inappropriate
value of sense resistor. See the Sense Resistor section.
5. A poor load regulation can have many causes. You
should first check the voltages and signals at the critical
pins.
6. The VREF pin should be at the voltage set by the VID
pins. If the power supply pins are correct and the VID
pins are correct, the VREF should be at the correct volt-
age.
7. Next check the oscillator pin. A saw tooth wave at the
frequency set by the external capacitor should be seen.
8. When the VREF and CEXT pins are determined to be
correct and the output voltage is still incorrect look at
the waveform at VCCQP. This pin should be swinging
from ground to +12V (in the +12V application) and
from slightly below +5V to about +10V (charge pump
application). If the VCCQP pin is noisy, with ripples and
overshoots, then the noise may cause the converter to
function improperly.
9. Next, look at the HIDRV pin. This pin directly drives the
gate of the FET. It should provide a gate drive (Vgs) of
about 5V when turning the FET on. A careful study of
the layout is recommended. See the PCB Layout Guide-
lines and Considerations section.
10. Experience shows that the most frequent errors are using
incorrect components, improper connections, and poor
layout.
Performance Evaluation
This section shows the results of a random sample evalua-
tion. Use these results as a reference guide for evaluating the
RC5040 DC-DC converter for Pentium Pro motherboards.
Load Regulation
VID I
load
(A) V
out
(V)
0100 0.5 3.0904
1.0 3.0825
2.0 3.0786
3.0 3.0730
4.0 3.0695
5.0 3.0693
6.0 3.0695
7.0 3.0695
8.0 3.0694
9.0 3.0694
9.9 3.0691
Load Regulation 0.5A – 9.9A 0.70%
VID I
load
(A) V
out
(V)
0010 0.5 3.2805
1.0 3.2741
2.0 3.2701
3.0 3.2642
4.0 3.2595
5.0 3.2597
6.0 3.2606
7.0 3.2611
8.0 3.2613
9.0 3.2611
10.0 3.2607
11.0 3.2599
12.0 3.2596
12.4 3.2596
Load Regulation 0.5A – 12.4A 0.64%