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HPA5150A Adapter Overview
Interface Descriptions
Chapter 1 11
Interface Descriptions
This section provides greater detail about the PCI, SCSI, and Wide
Ultra2 SCSI interfaces.
The PCI Interface
PCI is a high-speed standard local bus for interfacing a number of I/O
components to a processor and memory subsystem. The PCI
functionality for the A5150A is contained within the I/O Processor Chip.
The adapter connects directly to the PCI bus and generates timing
protocol in compliance with the PCI application.
The PCI interface operates as a 32-bit or 64-bit DMA bus master. The
connection is made through the edge connector J1 (see Figure 1-1 on
page 9). The signal definitions and pin numbers conform to the PCI Local
Bus Specification Revision 2.1 standard. The A5150A conforms to the
PCI universal signaling environment for a 5 volt or 3.3 volt PCI bus.
The SCSI Interface
The SCSI functionality for the A5150A is contained within the PCI-SCSI
I/O Processor Chip. The adapter connects directly to the two SCSI buses
for 16-bit SE or LVD SCSI applications and generates timing and
protocol in compliance with the SCSI standard. Each SCSI interface
operates at a burst transfer rate of up to 40 MBytes per second for wide
single-ended transfers, and up to 80 MBytes per second for wide LVD
SCSI transfers.
The two SCSI interfaces on the host bus adapter card operate as 16-bit,
synchronous or asynchronous, single-ended or LVD, and support Ultra2
SCSI protocols and 16-bit arbitration. The interface is made through
connectors J2 and J5 for channel A and J3 and J4 for channel B.
Connectors J2 and J3 are 68-pin, VHDCI right- angle receptacles that
protrude through the ISA/EISA bracket.
The adapter supplies SCSI bus TERMPWR (termination power) through
a blocking diode and auto-resetting current-limiting device. Each SCSI
channel has two LEDs to indicate the terminator’s power (TERMPWR)
status. The TERMPWR Good (Channel A or B) LED indicates when the
termination power is above 3.0 volts. The TERMPWR Shorted LED