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Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC
®
970MP RISC Microprocessor
AppNote_970FX-MP_Differences_Body.fm.1.0
November 15, 2006
5. Design Enhancements for PowerPC 970MP
Page 15 of 25
If the expected results are not observed, an error is flagged in the status register. The DIAG_RDT vector out
of the receiver provides observability of individual channel failures. The status register, bit 1, also indicates
that the shorts test is complete. Completion of the shorts test within a reasonable period of time should be
verified after the test is initiated with SCOM mode reg ESTMODE and WIAP.
5.2.2.4 Receiver Random Data Self Test
Also discussed in the transmitter description is the Pseudo-Random Data Test (RDT). The receiver also has
an LFSR register built into it, that is capable of duplicating the pseudo-random test patterns that were sent
across the link from the transmitter core. Preceding the random pattern across the link is a solid 0 value.
When the random data self test is initiated within the receiver by enabling the SCOM mode reg RDTMODE
and RIAP, the receiver self-test logic monitors the data received, and when a transition from the solid ‘0’ value
to a ‘1’ is observed, the receiver LFSR register begins to generate patterns which are then compared to the
received data. Once initiated, the random data self-test procedure continues until RDTMODE and RIAP are
disabled.
The following is the process for performing a link random data self test:
• 1. Train the receiver.
• 2. Force the transmitter to send data 0’s.
• 3. Wait for the receiver to be flushing 0’s.
• 4. Start receiver SCOM mode reg RDTMODE and RIAP set active.
• 5. Start transmitter SCOM mode reg RDTMODE and WIAP set active (starts the test).
• 6. Receiver status reports errors if the test fails.
If the expected results are not observed on any channel, an error is flagged in the status register. The
DIAG_RDT vector out of the receiver provides observability of any channel which did not contain expected
values for the duration of the test. Unlike the shorts test previously described, the status register will never
indicate completion of the test, as there is no predefined end to the random data sequence.
For status information to remain valid at the termination of a test, the random data self test should be termi-
nated by deasserting RIAP at the receiver prior to deasserting WIAP at the transmitter. However, since there
is no indication that the random data self test ever started within the receiver, WIAP can be deasserted first,
which provokes errors on all receiver channels upon its deassertion. Status and DIAG_RDT should be moni-
tored before deasserting WIAP to verify that there are no failing channels prior to its deassertion.
The LFSR data sent across the link represents data with a rich mix of data transitions that are much more
random than the IAP training pattern, and therefore stress the link alignment beyond the point that it was
stressed during IAP. A link which successfully completes IAP may still suffer from bit errors when random
data is transferred across the link. Random data self test allows the link to be evaluated for proper alignment
before real data is sent across the link.
5.2.3 Bus Configuration
The larger L2 caches, the bus arbiter between the two cores, and the use of the PI receiver design combine
to introduce additional delay in the path between the L2 cache and the bus interface. In particular, the PI
receiver adds one bus beat of delay, and the bus arbiter adds another bus beat of delay on incoming signals.
The bus arbiter adds two bus beats of delay on the outgoing signals. This results in an additional four bus
beats of latency for a snoop response, for example. The programmable delay parameters described in