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50 PC 300 GL and 300 PL
DMA I/O address map
Table 34. DMA I/O address map
Address (hex) Description Bits Byte pointer
0000 Channel 0, Memory Address register 00–15 Yes
0001 Channel 0, Transfer Count register 00–15 Yes
0002 Channel 1, Memory Address register 00–15 Yes
0003 Channel 1, Transfer Count register 00–15 Yes
0004 Channel 2, Memory Address register 00–15 Yes
0005 Channel 2, Transfer Count register 00–15 Yes
0006 Channel 3, Memory Address register 00–15 Yes
0007 Channel 3, Transfer Count register 00–15 Yes
0008 Channels 0–3, Read Status/Write Command
register
00–07
0009 Channels 0–3, Write Request register 00–02
000A Channels 0–3, Write Single Mask register bits 00–02
000B Channels, 0–3, Mode register (write) 00–07
000C Channels 0–3, Clear byte pointer (write) N/A
000D Channels, 0–3, Master clear (writer)/temp (read) 00–07
000E Channels 0–3, Clear Mask register (write) 00–03
000F Channels 0–3, Write All Mask register bits 00–03
0081 Channel 2, Page Table Address register 00–07
0082 Channel 3, Page Table Address register 00–07
0083 Channel 1, Page Table Address register 00–07
0087 Channel 0, Page Table Address register 00–07
0089 Channel 6, Page Table Address register 00–07
008A Channel 7, Page Table Address register 00–07
008B Channel 5, Page Table Address register 00–07
008F Channel 4, Page Table Address/Refresh register 00–07
00C0 Channel 4, Memory Address register 00–15 Yes
00C2 Channel 4, Transfer Count register 00–15 Yes
00C4 Channel 5, Memory Address register 00–15 Yes
00C6 Channel 5, Transfer Count register 00–15 Yes
00C8 Channel 6, Memory Address register 00–15 Yes
00CA Channel 6, Transfer Count register 00–15 Yes
00CC Channel 7, Memory Address register 00–15 Yes