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Appendix A. Connector pin assignments
Appendix A. Connector pin assignments
The following figures show the pin assignments for various system board connectors.
Monitor connector
5
1
10 6
15 11
1
C1 C2
C3
C5
C4
Figure 15. Monitor port connector pin assignments—SVGA
Pin Signal I/O Pin Signal I/O
1 Red O 2 Green O
3 Blue O 4 Monitor ID 2 - Not
used
I
5 Ground NA 6 Red ground NA
7 Green ground NA 8 Blue ground NA
9 +5 V, used by DDC2B NA 10 Ground NA
11 Monitor ID 0 - Not
used
I 12 DDC2B serial data I/O
13 Horizontal sync O 14 Vertical sync O
15 DDC2B clock I/O
Figure 16. Monitor port connector pin assignments—DVI main pin field
Pin Signal I/O Pin Signal I/O
1 TMDS data 2+ O 2 TMDS data 2- O
3 TMDS data 2/4 return N/A 4 TMDS data 4-* O
5 TMDS data 4+* O 6 DDC clock I/O
7 DDC data I/O 8 Analog vertical sync O
9 TMDS data 1- O 10 TMDS data 1+ O
11 TMDS data 1/3 shield N/A 12 TMDS data 3+* O
13 TMDS data 3+* O 14 +5V power O
15 Ground N/A 16 Hot plug detect O
17 TMDS data 0- O 18 TMDS data 0+ O
19 Return N/A 20 TMDS D5* O
21 TMDS data 5+* O 22 TMDS clock shield N/A
23 TMDS clock+ O 24 TMDS clock- O
Copyright IBM Corp. September 1999 25