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Appendix C. IRQ and DMA channel assignments
Appendix C. IRQ and DMA channel assignments
The following figures list the interrupt request (IRQ) and direct memory access (DMA) channel
assignments.
Figure 38. IRQ channel assignments
IRQ System resource
NMI Critical system error
SMI System management interrupt — power management
0 Reserved (interval timer)
1 Reserved (keyboard)
2 Reserved, cascade interrupt from slave PIC
3 COM2
3
4 COM1
3
5 LPT2/audio (if present)
6 Diskette controller
7 LPT1
3
8 Real-time clock
9 Video
10 Available to user
11 Available to user
12 Mouse port
13 Reserved (math coprocessor)
14 Primary IDE (if present)
15 Secondary IDE (if present)
Figure 39. DMA channel assignments
DMA channel Data width System resource
0 8 bits Open
1 8 bits Open
2 8 bits Diskette drive
3 8 bits Parallel port (for ECP or EPP)
4 – Reserved (cascade channel)
5 16 bits Open
6 16 bits Open
7 16 bits Open
3
Default, can be changed to another IRQ.
40 Copyright IBM Corp. September 1999