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CHAPTER 3 CPU ARCHITECTURE
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled
with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specify flag.
The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request
is acknowledged, and set to 1 when the EI instruction is executed.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the
vectored interrupt request whose priority is specified by the priority specify flag registers (PR0L, PR0H,
and PR1L) (Refer to 12.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is
disabled. Whether the interrupt request is actually acknowledged is controlled by the status of the interrupt
enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.