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Specification Update 41
BV71. PCIe* Root Port May Not Initiate Link Speed Change
Problem: The PCIe Base specification requires the upstream component to maintain the PCIe link
at the target link speed or the highest speed supported by both components on the
link, whichever is lower. PCIe root port will not initiate the link speed change without
being triggered by the software when the root port maximum link speed is configured
to be 5.0 GT/s. System BIOS will trigger the link speed change under normal boot
scenarios. However, BIOS is not involved in some scenarios such as link disable/re-
enable or secondary bus reset and therefore the speed change may not occur unless
initiated by the downstream component. This erratum does not affect the ability of the
downstream component to initiate a link speed change. All known 5.0Gb/s-capable
PCIe downstream components have been observed to initiate the link speed change
without relying on the root port to do so.
Implication: Due to this erratum, the PCIe root port may not initiate a link speed change during
some hardware scenarios causing the PCIe link to operate at a lower than expected
speed. Intel has not observed this erratum with any commercially available platform.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV72. Successive Fixed Counter Overflows May be Discarded
Problem: Under specific internal conditions, when using Freeze PerfMon on PMI feature (bit 12 in
IA32_DEBUGCTL.Freeze_PerfMon_on_PMI, MSR 1D9H), if two or more PerfMon Fixed
Counters overflow very closely to each other, the overflow may be mishandled for some
of them. This means that the counter’s overflow status bit (in
MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally,
PMI interrupt may be missed if software programs a counter in Sampling-Mode (PMI bit
is set on counter configuration).
Implication: Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is
used.
Workaround: Software can avoid this by:
1. Avoid using Freeze PerfMon on PMI bit
2. Enable only one fixed counter at a time when using Freeze PerfMon on PMI
Status: For the steppings affected, see the Summary Tables of Changes.
BV73. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a
#NM Exception
Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (Invalid-
Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-not-
available) exception will be raised instead of #UD exception.
Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround: Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status: For the steppings affected, see the Summary Tables of Changes.