Filter
Top Products
46 Specification Update
BV88. Concurrently Changing the Memory Type and Page Size May Lead to a
System Hang
Problem: Under a complex set of microarchitectural conditions, the system may hang if software
changes the memory type and page size used to translate a linear address while a TLB
(Translation Lookaside Buffer) holds a valid translation for that linear address.
Implication: Due to this erratum, the system may hang. Intel has not observed this erratum with
any commercially available software.
Workaround: None identified. Please refer to Software Developer’s Manual, volume 3, section
“Recommended Invalidation” for the proper procedure for concurrently changing page
attributes and page size.
Status: For the steppings affected, see the Summary Tables of Changes.
BV89. MCI_ADDR May be Incorrect For Cache Parity Errors
Problem: In cases when a WBINVD instruction evicts a line containing an address or data parity
error (MCACOD of 0x124, and MSCOD of 0x10), the address of this error should be
logged in the MCi_ADDR register.
Due to this erratum, the logged address may be
incorrect, even though MCi_Status.ADDRV (bit 63) is set.
Implication: The address reported in MCi_ADDR may not be correct for cases of a parity error found
during WBINVD execution.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV90. During Package Power States Repeated PCIe* and/or DMI L1
Transitions May Cause a System
Problem: Under a complex set of internal conditions and operating temperature, when the
processor is in a deep power state (package C3, C6 or C7) and the PCIe and/or DMI
links are toggling in and out of L1 state, the system may hang.
Implication: Due to this erratum, the system may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV91. Instruction Fetches Page-Table Walks May be Made Speculatively to
Uncacheable Memory
Problem: Page-table walks on behalf of instruction fetches may be made speculatively to
uncacheable (UC) memory.
Implication: If any paging structures are located at addresses in uncacheable memory that are used
for memory-mapped I/O, such I/O operations may be invoked as a result of speculative
execution that would never actually occur in the executed code path. Intel has not
observed this erratum with any commercially available software.
Workaround: Software should avoid locating paging structures at addresses in uncacheable memory
that are used for memory-mapped I/O.
Status: For the steppings affected, see the Summary Tables of Changes.