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8 Specification Update
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of a table row indicates this erratum is either new or modified from
the previous version of the document.
Errata (Sheet 1 of 5)
Number
Steppings
Status ERRATA
E-1 L-1 N-0
BV1
XXXNo FixThe Processor May Report a #TS Instead of a #GP Fault
BV2
XXXNo Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations.
BV3
XXXNo FixIO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
BV4
XXXNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values
BV5
XXXNo Fix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
BV6
XXXNo Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions