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Specification Update 43
BV77. PCIe* Controller May Not Enter Loopback
Problem: The PCIe controller is expected to enter loopback if any lane in the link receives two
consecutive TS1 ordered sets with the Loopback bit set. Due to this erratum, if two
consecutive TS1 ordered sets are received only on certain lanes, the controller may not
enter loopback.
Implication: Intel has not observed any functional issue with any commercially available PCIe
devices.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.
BV78. Link Margin Characterization May Hang Link
Problem: The processor supports tools and mechanisms to characterize and measure margins for
the PCIe interface. Due to this erratum, when performing link margin-to-failure
characterization, it is possible that a high bit error rate may cause the link to hang.
Implication: Under extreme conditions, poor link quality during link characterization may result in
processor hang. Intel has not observed this erratum with any commercially available
platforms under normal operating conditions.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV79. Unused PCIe* Lanes May Report Correctable Errors
Problem: Due to this erratum, during PCIe* link down configuration, unused lanes may report a
Correctable Error Detected in Bus 0, Device 1, Function 0-2, and Device 6, Function 0,
Offset 158H, Bit 0.
Implication: Correctable Errors may be reported by a PCIe controller for unused lanes.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV80. RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information
Problem: When CPUID.0AH:EAX[15:8] reports 8 general-purpose performance monitoring
counters per logical processor, RDMSR of IA32_PERFEVTSEL{4-7} (MSR 18AH-18DH)
may not return the same value previously written by software.
Implication: Software should not rely on values read from these MSRs.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.