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User’s Manual
8 ECB-870 User’s Manual
2.3.3 AGP Interface
A single AGP component or connector (not both) is supported by the MCH AGP interface.
The AGP buffers operate only in 1.5 V mode. They are not 3.3 V safe. The AGP interface
supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to system
memory are not snooped on the system bus. PCI semantic cycles to system memory are
snooped on the system bus. The MCH supports PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism
must be selected during system initialization. Both upstream and downstream addressing
is limited to 32 bits for AGP and AGP/PCI transactions. The MCH contains a 32 deep AGP
request queue. High-priority accesses are supported. All accesses from the AGP/PCI
interface that fall within the Graphics Aperture address range pass through an address
translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and
hub interface are limited to memory writes originating from the hub interface destined for
AGP. The AGP interface is clocked from a dedicated 66 MHz clock
(66IN). The AGP-to-host/core interface is asynchronous.
2.3.4 SiS 315 4X AGP VGA controller
SiS315 is the the second chip of the SiS 256-bit graphics accelerator family. With a 529-
pin PBGA package, SiS315 integrates a 4X/2X AGP controller with full sideband or
pipeline support, a 256-bit 3D/2D graphics engine and a motion compensation MPEG
I/MPEG II accelerator. It offers a complete 128-bit SDR/DDR memory data bus.
Embedded with a 128-bit 2D engine, it can achieve ultra high 2D performance with the
maximum memory bandwidth up to 5.3 GB/s. An optimized 3D pipeline architecture is
implemented for eliminating the overhead resulted from texture read, Z-buffer read/write
and destination read latencies and achieving a sustain throughput of over 90% of peak
throughput even when texture, Z buffer and alpha blending functions are all enabled.
SiS315 also includes a video accelerator and a high performance DVD motion
compensation logic to provide very smooth DVD playback. SiS315 provides 12-bit DDR
(dual data rate) or single 24-bit SDR digital interface to support secondary display, which
is independent of primary CRT display. The digital video interface can also support
different TV encoders or LCD transmitters offered by the third party vendors.
2.3.5 PCI Interface
The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up
to six external PCI bus masters in addition to the internal ICH2 requests.