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82543GC Gigabit Ethernet Controller Specification Update
11
SPECIFICATION CHANGES
1. GMII Setup and Hold Times
Problem: The data sheet contains incorrect setup and hold time specifications for the GMII interface.
The old setup and hold times were 2.5ns minimum and 4ns. typical.
For the receive signals, the new setup time is 2.0ns. (min.) the new hold time is 0ns. (min.). For the transmit
signals, the new setup time is 2.5ns. (min.) and the new hold time is 0.5ns. (min.) Documentation will change to
show the new values.
Affected Specs: AC Timings section of 82543GC Gigabit Ethernet Controller Datasheet Rev. 2.02.
ERRATA
1. MDI Control Register Returns Incorrect Values
Problem: MDIO reads through the MDI control register return wrong values.
Implication: The Management Data Interface register is necessary for the controller to communicate serially with GMII/MII
PHY devices through the B_MDIO pin.
Workaround: Route MDIO and MDC pins from an external PHY device to B_SDP (Software Defined) pins and add
appropriate software to capture the MDI data.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
2. Descriptor Queue Maximum Size Limitation
Problem: When the 82543GC device initiates a PCI cycle to access data, it is possible for the target to issue a “retry”. A
retry is a target disconnect without data transfer. In response, the 82543GC controller may attempt another read
or write cycle to a different address instead of retrying the same memory location. In a PC environment, it is
possible that the target chipset will hang, generate an NMI or exhibit other errors.
Implication: This erratum affects the 82543 device’s ability to access data correctly from the descriptor list using its DMA
process.
Workaround: Do not allow the controller to have more than 256 active descriptors in either the receive descriptor ring or the
transmit descriptor ring. In other words, program the device so the receive tail register does not exceed the
receive head register by more than 0x100 and the transmit tail register does not exceed the transmit head
register my more than 0x100. There are two ways to achieve this goal:
• Set up the software driver to never manage more than 256 descriptors per ring.
• Program the driver to actively calculate the difference between descriptor head and tail. This way, the
software driver can manage many more total descriptors, but it never moves the tail pointer far
enough to make excessive descriptors active.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
3. Late Collision Statistics May Be Incorrect
Problem: In gigabit half duplex mode, the late collision statistic register may not count late collision events correctly.
Implication: The actual number of late collisions in half duplex mode may be higher than reflected in the statistic register.