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82543GC Gigabit Ethernet Controller Specification Update
14
Workaround: None.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
13. Zero-Byte PCI Bus Writes
Problem: The 82543GC Gigabit Ethernet Controller can generate zero-byte writes on a 32-bit PCI bus because it is has a
64-bit internal architecture. A zero-byte access is defined as a data transfer with IRDY# and TRDY# asserted
but none of the byte enables asserted.
Implication: Zero-byte writes are allowed by the PCI specification. However, an erratum in the 450GX PC chipset causes
incompatibility with the 82543GC controller. The erratum is titled, #29 Hang with Zero-Byte Write Followed by a
Nonzero-Byte Write. The erratum states, “If an inbound PCI zero-byte write is followed by a PCI nonzero-byte
write, and a specific set of timing circumstances exist, the chipset can become out of sync.”
Workaround: In a 450GX chipset system, change the system’s IOQ depth from eight to one. In most systems, the IOQ depth
parameter is accessible through the BIOS setup utility.
Status: Intel does not plan to resolve this problem in a future stepping of the 82543GC Gigabit Ethernet Controller.
14. TCP Segmentation Feature Operates Incorrectly
Problem: Several errata prevent proper TCP segmentation operation, in particular, concurrency with other DMA events
and payload mismatch trapping. At least one of the errata can cause transmit operation to hang.
Implication: Do not use the TCP segmentation feature.
Workaround: None.
Status: Some of the errata were corrected in the A1 stepping. At least one severe transmit problem was not corrected.
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
15. Incorrect Checksum Calculation and Indication
Problem: Several errata can cause checksum calculations (packet, TCP, UDP, IP, etc.) to be performed incorrectly or to
be misreported. These problems can occur on both transmitted and received packets and can also relate to
packet size.
Implication: Checksum offloading is not reliable and should not be used.
Workaround: None. Checksums should be calculated in software rather than being offloaded to 82543GC hardware.
Status: Some of the problems were corrected in the A1 stepping, including the problem of incorrect UDP checksum
indication. The remaining problems were corrected in the A2 stepping, with the exception of receive IP
checksum. See erratum #23, “Receive IP Checksum Offload Disabled.”
16. Transmitter Affected by Discarding Packets
Problem: When the 82543GC device is forced to discard a transmit packet because of non-transmission, internal pointers
may get corrupted and lead to bad packet transmission or a hang condition. The situations that can trigger this
behavior are:
(a.) Half-duplex operation and the number of collisions exceeds the programmed threshold.
(b.) Half–duplex operation and a late collision occurs with re-transmit disabled for late collisions.
(c.) Transmit underrun with re-transmit disabled for underruns.
Implication: Precautions must be taken so that the 82543GC device does not discard packets it cannot transmit.