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82543GC Gigabit Ethernet Controller Specification Update
4
27. Link Status Change Interrupt Only Occurs If Link is Up ....................................................................17
28. Early Transmit Feature Does Not Operate Correctly.........................................................................17
29. TDO Output Not Floated When JTAG TAP Controller Inactive.........................................................18
30. Initialization Ignores Incorrect EEPROM Signature...........................................................................18
31. Internal Loopback Difficulties.............................................................................................................18
32. Collision Pin Not Ignored in TBI Mode...............................................................................................18
33. Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers..............................19
34. Illegal Oversize Packets Overflow Receive FIFO..............................................................................19
35. Transmit Descriptor Writeback Problems with Non-Zero WTHRESH ...............................................19
36. Bus Initialization with Some Chipsets................................................................................................20
37. Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups ...........................20
38. Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000............................................20
SPECIFICATION CLARIFICATIONS................................................................................................................21
1. 0-70C Ambient Temperature Range .................................................................................................21
2. Receiver Enabling and Disabling.......................................................................................................21
DOCUMENTATION CHANGES........................................................................................................................21
1. TX/RX Descriptor Register Addresses ..............................................................................................21
2. Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set.......................................................22
3. Values Programmed to Some Registers While in Reset Do Not Persist...........................................22
4. JTAG Port Operation.........................................................................................................................22
5. Register Summary Uses Improper Page Reference Format.............................................................23
6. Change O_EN_CDET Output to NO_CONNECT .............................................................................23
7. Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T ......................23
8. Remove Transmit Report Status Sent Function................................................................................23
9. Remove Transmit DMA Pre-fetching and Preemption Functions......................................................23
10. Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT).....................................24
11. Remove Adaptive IFS Throttle Function (AIT)...................................................................................24