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82543GC Gigabit Ethernet Controller Specification Update
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Workaround: None.
Status: This erratum was resolved in the A1 stepping of the 82543GC Gigabit Ethernet Controller.
4. Some Registers Cannot Be Accessed During Reset
Problem: PCI accesses to transmit descriptor registers will not succeed if the 82543GC controller is in a transmit reset
state. Similarly, PCI accesses to receive descriptor registers will not succeed if the 82543GC controller is in a
receive reset state. Affected registers include the transmit descriptor registers (offsets 0x420 – 0x440), receive
descriptor registers, diagnostic packet buffer head/tail registers (offsets 0x8000 – 0x8018) and the flow control
threshold registers (offsets 0x160 – 0x168).
Implication: Accesses to any of these registers during reset states will result in an infinite PCI retry state.
Workaround: Software can check that the 82543GC device is not in a reset state before accessing the registers.
Status: Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. However, software
still should not attempt to write to these registers during reset states because the data written will not be
retained. Documentation will be updated to specify which registers are held in reset during which conditions.
See Documentation Change #3.
5. DAC Accesses May Be Interpreted Incorrectly
Problem: When the 82543GC device is mapped to a 64-bit PCI address space as a target device, it does not always
handle dual-address cycle (DAC) accesses correctly.
Implication: The 82543GC Gigabit Ethernet Controller is designed to function with addresses above the 4 GByte PCI
boundary and can advertise this capability in base address register 0. As a bus master, it can fully utilize this
space and initiates all 64-bit DAC cycles correctly. However, it does not always respond to DAC cycles correctly
as a target device. In addition, accesses to flash memory may work incorrectly. See Erratum #7, Flash Memory
Functions Incorrectly in 64-Bit Address Space.
Workaround: Bit 0x0D in the EEPROM space at byte 0x0A denotes 64-bit address mapping if cleared to “0”. (This is the
default configuration.) Program the bit to logic “1” to denote 32-bit address space. As an added precaution,
software drivers can check this bit and render a shutdown with an error message if a “0” is detected.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
6. Flash Memory Interface Functions Incorrectly in 64-Bit Address Space
Problem: When the 82543GC controller is mapped to a 64-bit address space as a target, the flash memory space is also
mapped to a 64-bit space. However, the flash memory interface hardware is implemented for 32 bit addressing
and may fail in response to 64-bit addressing.
Implication: This erratum is directly related to Erratum #5 (DAC Accesses May Be Interpreted Incorrectly). Mapping flash
memory to an address above 4 GBytes may result in PCI master aborts or other incorrect behavior.
Workaround: The workaround is identical to the workaround for Erratum #5, DAC Accesses May Be Interpreted Incorrectly.
Bit 0x0D in the EEPROM space at byte 0x0A denotes 64-bit address space if cleared to “0”. (This is the default
configuration.) Program this bit to logic “1” to denote 32-bit address space. As an added precaution, software
drivers can check this bit and render a shutdown with an error message if a “0” is detected.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
7. Excessive Errors in 100Mb Half-Duplex Mode
Problem: When the 82543GC Gigabit Ethernet Controller operates in 100Mb mode and network traffic causes collisions,
the device will experience excessive CRC, alignment and RX_ERR errors. Intel observed late collision
situations where the 82543GC device attempted packet transmission while another station was transmitting and
after the collision window expired. The observed error rates were approximately one error per 300 good
received packets. Error rates this high cause excessive packet loss, which can lead to protocol timeouts. The
problem occurs with multiple PHY devices and a variety of Ethernet hub and cabling configurations.