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Intel
®
IQ31244 Customer Reference Board
18 User’s Manual
3.1 Interrupts
The Intel
®
80321 I/O Processor is built around an Intel XScale
®
core, which has four external
interrupt lines designated XINT0# through XINT3#. In the 80321 processor, these interrupt lines
are not directly connected to external interrupts, but pass through a layer of external interrupt
routing logic. Figure 4 shows the interrupt connections on the processor.
The external devices are AND-gated into designated interrupt signals. Therefore, the specific
device that generates the interrupt cannot be detected. However, the eight GPIO pins of the Intel
®
31154 133 MHz PCI Bridge are used to read interrupts from the specific device, as shown in
Table 8.
Figure 4. Intel
®
80321 I/O Processor Interrupt Connections
Table 8. Intel
®
31154 133 MHz PCI Bridge GPIO Pin Assignments
GPIO Signal
7 SATA 3 Interrupt
6 SATA 2 Interrupt
5 SATA 1Interrupt
4 SATA 0 Interrupt
0 Expansion Slot INTB#