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Evaluation Platform Board Manual 51
Intel
®
IQ80332 I/O Processor
IQ80321 and IQ80332 Comparisons
IQ80321 and IQ80332 Comparisons A
This appendix provides a brief description for differences between IQ80332 and IQ80321. Please
also refer to application note: Intel
®
80321 Software Conversion to the Intel
®
80332 I/O Processor
Application Note.
Table 42. Intel
®
IQ80321 Evaluation Platform Board and Intel
®
IQ80332 I/O processor
evaluation platform board Comparisons
Features
Intel
®
IQ80332 I/O Processor Evaluation
Platform Board
Intel
®
IQ80321 Evaluation Platform Board
I/O Processor 80332 Intel
®
80321 I/O Processor
Core/Microprocessor
Technology
Intel XScale® microarchitecture Intel XScale® microarchitecture
Memory Technology DDRII 400 MHz SDRAM DIMM PC1600 DDR SDRAM (100 MHz Clock)
Form Factor
PC board that attaches to a PC/Server/Backplane
by a PCI Express slot – Two PCI-X Expansion Slot
Extended PC board that attaches to a
PC/Server/Backplane – One PCI-X Expansion Slot
PC/Server/Backplane
Connection
PCI Express
PCI-X 133 MHz/64-Bits or
PCI 66 MHz/64 Bits
Expansion Card Slot
One PCI-X 100 MHz/64-bits
One PCI-X 2.0 266 MHz/64-bit
One PCI-X 133 MHz/64-bit
PCI/PCI-X Bridge
PCI-X to PCI-X Bridge integrated with the
IQ80332l
IBM PCI-X Bridge
Reference: IBM 133 PCI-X Bridge
http://www.chips.ibm.com/
Interrupt Routing
External interrupts are routed through the XINT
pins on the 80332. Please see Table 9 for more
details.
External interrupts are routed through the XINT
pins on the 80321. They include INTA, INTB form
PCI-X expansion slot, INTA from 82544 GBE, and
UART interrupt – Steering and Status registers are
in 80321 – see Intel
®
80321 I/O Processor
Developer’s Manual
Timers
Internal to 80332 – Refer to Intel
®
80332 I/O
Processor Developer’s Manual
Internal to the 80321 - please refer to the Intel
®
80321 I/O Processor Developer’s Manual
Local/Peripheral Bus
66 MHz multiplexed bus with two chip-enables,
Synch/Asynchronous (80332 operates in 66 MHz
Asynchronous mode) – Refer to PBI section in
Intel
®
80332 I/O Processor Developer’s Manual
2-bit/33-100MHz multiplexed bus with six
chip-enables, Synch/Asynchronous (IQ80321
operates in 33 MHz Asynchronous mode) –
Refer to PBI section in the IIntel
®
80321 I/O
Processor Developer’s Manual.
Flash Memory
8-bit or 16-bit, 8 MB accessed through Peripheral
Bus with chip-enable 0 (PCE0)
16-bit, 8 MB accessed through Peripheral Bus
with chip-enable 0 (PCE0))
Serial Debug Port Two UARTs integrated within the 80332.
One UART on the Peripheral bus – 16C550
device
Network Debug Port Intel® 82545EM GbE on the 100 MHz PCI-X bus Intel® 82544 GbE on the PCI-X bus
Rotary Switch Same Same
LED HEX Display Same Same
JTAG 20-PIN ARM Compliant 20-PIN ARM Compliant
Logic Analyzer Connection Through PCI-X or PCI Express Various Mictors