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5-4 IQ80960RM/RN
Evaluation Board Manual
MON960 Support for IQ80960RM/RN
By default, Primary Outbound Configuration Cycle parameters are not established. The ATU
Configuration Register (ATUCR) is initialized to establish the operational parameters for the
Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and
secondary ATUs. The PCI host is responsible for allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.
5.2.7 PCI-to-PCI Bridge Initialization
PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the
PCI host processor. Local initialization occurs first and consists mainly of establishing the operational
parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN
platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host
configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register
(SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during
conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration
cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating
transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for
assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values.
5.2.8 Secondary ATU Initialization
Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters
for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The
Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base
address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention,
the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The
Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of
memory required by the secondary ATU. The SIALR value is based on the installed SDRAM
configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to
establish the translation value for Secondary PCI-to-Local accesses. The SIATVR value is set to
reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register
(SOMWVR) is initialized to establish the translation value for Local-to-Secondary PCI accesses.
The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to
access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window
Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map.
On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as
such, is required to configure the devices of the secondary PCI bus. Secondary Outbound
Configuration Cycle parameters are established during secondary PCI bus configuration.
Secondary PCI bus configuration is accomplished via MON960 Extension routines.