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Timers
16-Bit Timer Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
126
Panasonic
TM4MD/TM5MD: Timer n Mode Register x’00FE80’/x’00FE90’
TMnEN: TMnBC count
0: Disable
1: Enable
TMnNLD: TMnBC, T flip-flop, and S-R flip-flop operation select
0: Set all to 0 (initialize)
1: Operate all
TMnUD[1:0]: Timer n up/down counter mode select
Ignored when two-phase encoding is selected.
00: Up counter
01: Down counter
10: Up when TMnIOA is high; down when low
11: Up when TMnIOB is high; down when low
TMnTGE: External trigger enable for start count
0: Disable
1: Start count at falling edge of TMnIOB
TMnONE: Counter operating mode select
0: Repeat (except with PWM output)
1: One-shot pulse (counter stops on the next clock after TMnBC = TMnCA)
TMnMD[1:0]: TMnCA and TMnCB operating mode select
00: Compare register (single buffer)
01: Compare register (double buffer)
10: Capture register (TMnIOA high: capture A; TMnIOA low: capture B)
11: Capture register (TMnIOA high: capture A; TMnIOB high: captureB)
TMnECLR: Timer n BC external clear
0: Don’t clear
1: Clear TMnBC asynchronously when the TMnIC signal goes high.
TMnLP: Timer n BC loop select
0: 0000–FFFF
1: 0000–value in TMnCA
TMnASEL: TMnIOA output select
0: S-R flip-flop output (single-phase PWM)
1: T flip-flop output (two-phase PWM)
TMnS[2:0]: Timer n clock source select
000: Timer 0 underflow
001: Timer 1 underflow
010: TMnIB signal
011: B
OSC
/4
100: 4x two-phase encoder
101: 1x two-phase encoder
110, 111: Reserved
Bit:1514131211109876543210
TMn
EN
TMn
NLD
——
TMn
UD1
TMn
UD0
TMn
TGE
TMn
ONE
TMn
MD1
TMn
MD0
TMn
ECLR
TMn
LP
TMn
ASEL
TMn
S2
TMn
S1
TMn
S0
Reset:0000000000000000
R/W: R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W